clk: samsung: exynos5433: Add clocks for CMU_BUS{0|1|2} domains

This patch adds the mux/divider/gate clocks for CMU_BUS{0|1|2} domains
which contain global data buses clocked at up the 400MHz. These blocks
transfer data between DRAM and various sub-blocks. These clock domains
also contain global peripheral buses clocked at 67/111/200/222/266/333/400
MHz and used for register accesses.

Signed-off-by: Chanwoo Choi <[email protected]>
Acked-by: Inki Dae <[email protected]>
Reviewed-by: Pankaj Dubey <[email protected]>
Signed-off-by: Sylwester Nawrocki <[email protected]>

0 files changed, 0 insertions, 0 deletions