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authorNuno Sa <[email protected]>2024-10-29 14:59:41 +0100
committerStephen Boyd <[email protected]>2024-11-14 14:43:40 -0800
commit47f3f5a82a31527e027929c5cec3dd1ef5ef30f5 (patch)
tree9de268690a766ee5b6794588d017f52dbcae53ac /tools/perf/scripts/python/net_dropmonitor.py
parent9852d85ec9d492ebef56dc5f229416c925758edc (diff)
dt-bindings: clock: axi-clkgen: include AXI clk
In order to access the registers of the HW, we need to make sure that the AXI bus clock is enabled. Hence let's increase the number of clocks by one and add clock-names to differentiate between parent clocks and the bus clock. Fixes: 0e646c52cf0e ("clk: Add axi-clkgen driver") Signed-off-by: Nuno Sa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Conor Dooley <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
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