diff options
| author | Mark Rutland <[email protected]> | 2017-11-21 11:59:13 +0000 |
|---|---|---|
| committer | Will Deacon <[email protected]> | 2017-11-28 18:13:18 +0000 |
| commit | f81a348728ec5ac43f3bbcf81c97d52baba253f7 (patch) | |
| tree | 2be7b3bdfa04369661c86d7858bc0f280a08cd01 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323 (diff) | |
arm64: mm: cleanup stale AIVIVT references
Since commit:
155433cb365ee466 ("arm64: cache: Remove support for ASID-tagged VIVT I-caches")
... the kernel no longer cares about AIVIVT I-caches, as these were
removed from the architecture.
This patch removes the stale references to such I-caches.
The comment in flush_context() is also updated to clarify when and where
the TLB invalidation occurs.
Signed-off-by: Mark Rutland <[email protected]>
Cc: Catalin Marinas <[email protected]>
Cc: Will Deacon <[email protected]>
Signed-off-by: Will Deacon <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions