diff options
| author | Tao Ren <[email protected]> | 2022-05-09 19:56:15 +0200 |
|---|---|---|
| committer | Joel Stanley <[email protected]> | 2022-05-19 13:09:49 +0930 |
| commit | f3e5996218b6d81be5a503922793900dac3b1f99 (patch) | |
| tree | 0ad34b76b933bb707a2a87a47fba78962fbd9763 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | 4a92d02fce73af8e9932126dabd82a0c07e78290 (diff) | |
ARM: dts: aspeed-g4: Set spi-max-frequency for all flashes
Set "spi-max-frequency" to 50 MHz for all the flashes under the FMC
controller to ensure the clock frequency is calculated correctly.
Suggested-by: Cédric Le Goater <[email protected]>
Tested-by: Jae Hyun Yoo <[email protected]>
Signed-off-by: Tao Ren <[email protected]>
Signed-off-by: Cédric Le Goater <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Joel Stanley <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions