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| author | Marek Vasut <[email protected]> | 2022-11-04 17:03:14 +0100 |
|---|---|---|
| committer | Mark Brown <[email protected]> | 2022-11-10 17:52:44 +0000 |
| commit | ef55595548e13a5d61695bdf92e03df88c45994f (patch) | |
| tree | 8ba0c8790afc65077ab5d4f26d9e7f3d5b842f47 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | 81b6c043e7ba41e5a585f0d33213a32308d484ca (diff) | |
ASoC: dt-bindings: fsl-sai: Use minItems 5 for i.MX8MN clock and similar
The i.MX8MN currently uses "bus", "mclk0", "mclk1", "mclk2", "mclk3"
clock, which adds up to 5 clock total. Use minItems 5 for this setup.
Signed-off-by: Marek Vasut <[email protected]>
Acked-by: Rob Herring <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions