diff options
author | Benjamin Herrenschmidt <[email protected]> | 2018-07-03 17:24:47 +1000 |
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committer | Stephen Boyd <[email protected]> | 2018-07-06 10:53:20 -0700 |
commit | edc6f7e9b11d4ab54f80890dedf58a914cae61e4 (patch) | |
tree | 865bf30319c76585a09c638830b63b858928053a /tools/perf/scripts/python/mem-phys-addr.py | |
parent | 40dd71c75e395d9b0343f1e646de7ab5312540cc (diff) |
clk: aspeed: Treat a gate in reset as disabled
On some systems, we come out of the bootloader with some
gates set with the clock "enabled" but the reset also
asserted.
Since 8a53fc511c5e "clk: aspeed: Prevent reset if clock is enabled"
we check that enabled bit in aspeed_clk_enabled(), and do
nothing if already set.
This breaks when the above scenario occurs, as the clock
is enabled, but the reset still needs to be lifted.
This patch fixes it by also checking the reset bit (if any)
and treating a gate in "reset" as being disabled.
Signed-off-by: Benjamin Herrenschmidt <[email protected]>
Fixes: 8a53fc511c5e "clk: aspeed: Prevent reset if clock is enabled"
Cc: Eddie James <[email protected]>
Reviewed-by: Joel Stanley <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions