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authorSamuel Holland <[email protected]>2022-11-13 20:21:09 -0600
committerVinod Koul <[email protected]>2022-11-24 23:04:23 +0530
commite7a838694185c7d0965baa9ed2515f2e0ff8d502 (patch)
tree335c4f508005e029a497efd4a433edb83de963a8 /tools/perf/scripts/python/mem-phys-addr.py
parent5a0d2df462568486b85a88ed2c88ffbfa1645cd1 (diff)
dt-bindings: sun6i-a31-mipi-dphy: Add the A100 DPHY variant
A100 features an updated DPHY, which moves PLL control inside the DPHY register space. (Previously PLL-MIPI was controlled from the CCU. This does not affect the "clocks" property because the link between PLL-MIPI and the DPHY was never represented in the devicetree.) It also requires a modified analog power-on sequence. Finally, the new DPHY adds support for operating as an LVDS PHY. D1 uses this same variant. Acked-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Paul Kocialkowski <[email protected]> Signed-off-by: Samuel Holland <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
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