diff options
| author | Srujana Challa <[email protected]> | 2022-01-25 23:56:24 +0530 |
|---|---|---|
| committer | Herbert Xu <[email protected]> | 2022-02-05 15:10:50 +1100 |
| commit | e236ab0d43622a8a5a8ff06630fd467b444a9db9 (patch) | |
| tree | 0ed668ad75376ed14567465670f1a7b91bf7b170 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | 9eef6e972a32bc2454a22e8f0e8d4e7f55ff6613 (diff) | |
crypto: octeontx2 - increase CPT HW instruction queue length
LDWB is getting incorrectly used in HW when
CPT_AF_LF()_PTR_CTL[IQB_LDWB]=1 and CPT instruction queue has less than
320 free entries. So, increase HW instruction queue size by 320 and give
320 entries less for SW/NIX RX as a SW workaround.
Signed-off-by: Srujana Challa <[email protected]>
Signed-off-by: Shijith Thotton <[email protected]>
Signed-off-by: Herbert Xu <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions