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| author | Siddharth Vadapalli <[email protected]> | 2023-03-15 13:29:48 +0530 |
|---|---|---|
| committer | David S. Miller <[email protected]> | 2023-03-17 08:01:34 +0000 |
| commit | e0c9c2a7dd738120c2fbc155c6fba1066f109be0 (patch) | |
| tree | d9e4399b5325a0508bc0f6249fafa80fcd78dd9f /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | 40235edeadf58e4232bfcf8bf15be453cfe233b7 (diff) | |
dt-bindings: net: ti: k3-am654-cpsw-nuss: Add J784S4 CPSW9G support
Update bindings for TI K3 J784S4 SoC which contains 9 ports (8 external
ports) CPSW9G module and add compatible for it.
Signed-off-by: Siddharth Vadapalli <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions