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| author | Ville Syrjälä <[email protected]> | 2022-10-31 15:57:00 +0200 |
|---|---|---|
| committer | Ville Syrjälä <[email protected]> | 2022-11-02 08:53:59 +0200 |
| commit | dbea79a50221899e2c3b4be9967f535e89fd6d00 (patch) | |
| tree | d82673ad267d716704810e0dfa7df4b69ba4cdf5 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | 78e418d0ea7f74bca0c2312281a28de831ae8edf (diff) | |
drm/i915: Fix cs timestamp frequency for cl/bw
Despite what the spec says the TIMESTAMP register seems to
tick once every hrawclk (confirmed on i965gm and g35).
v2: Rebase
Signed-off-by: Ville Syrjälä <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Reviewed-by: Lionel Landwerlin <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions