diff options
| author | Andrew Jeffery <[email protected]> | 2019-06-28 12:08:36 +0930 |
|---|---|---|
| committer | Linus Walleij <[email protected]> | 2019-07-03 10:35:21 +0200 |
| commit | d0d88b5c9ed7cdc8f7d49b153d4ddc1bf1d8eb99 (patch) | |
| tree | f1cc8583d7d81cfc8b140640da4645252efc0dd5 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | 0290eba96be4325ad567b7e4e682ce3c937c9b7c (diff) | |
pinctrl: aspeed: Clarify comment about strapping W1C
Writes of 1 to SCU7C clear set bits in SCU70, the hardware strapping
register. The information was correct if you squinted while reading, but
hopefully switching the order of the registers as listed conveys it
better.
Cc: Johnny Huang <[email protected]>
Signed-off-by: Andrew Jeffery <[email protected]>
Acked-by: Joel Stanley <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions