diff options
| author | Peng Fan <peng.fan@nxp.com> | 2022-02-25 16:17:33 +0800 |
|---|---|---|
| committer | Abel Vesa <abel.vesa@nxp.com> | 2022-03-04 17:06:29 +0200 |
| commit | d097cc045b64948ca3048ced4a43cc74eaf641a5 (patch) | |
| tree | f9d29688d5de7aba0576727c19d15ecedc537f70 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | 38ce00adc16319544c8c56edd36324d2c1b98a50 (diff) | |
clk: imx8mp: remove SYS PLL 1/2 clock gates
Remove the PLL 1/2 gates as it make AMP clock management harder without
obvious benifit.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/20220225081733.2294166-4-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions