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author | Tony Lindgren <tony@atomide.com> | 2019-10-17 11:21:44 -0700 |
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committer | Tony Lindgren <tony@atomide.com> | 2019-10-18 08:45:32 -0700 |
commit | c7d8669f46ba97f6a8e14d6e9b8d6c39e2c07727 (patch) | |
tree | dd95cf5e0af1d35ff107643660cd40a5ba846bfd /tools/perf/scripts/python/mem-phys-addr.py | |
parent | 54ecb8f7028c5eb3d740bb82b0f1d90f2df63c5c (diff) |
bus: ti-sysc: Fix watchdog quirk handling
I noticed that when probed with ti-sysc, watchdog can trigger on am3, am4
and dra7 causing a device reset.
Turns out I made several mistakes implementing the watchdog quirk handling:
1. We must do both writes to spr register
2. We must also call the reset quirk on disable
3. On am3 and am4 we need to also set swsup quirk flag
I probably only tested this earlier with watchdog service running when the
watchdog never gets disabled.
Fixes: 4e23be473e30 ("bus: ti-sysc: Add support for module specific reset quirks")
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions