diff options
| author | Ben Skeggs <[email protected]> | 2020-11-12 12:29:43 +1000 |
|---|---|---|
| committer | Ben Skeggs <[email protected]> | 2020-11-14 14:35:57 +1000 |
| commit | be323a4cef022aa9685b08d5a94ddc841ccf617a (patch) | |
| tree | f01ee58a0f81a16f8eb00eae7a0a61bcce8ba8ff /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | 512bce50a41c528fa15c4c014293e7bebf018658 (diff) | |
drm/nouveau/ttm: avoid using nouveau_drm.ttm.type_vram prior to nv50
Pre-NV50 chipsets don't currently use the MMU subsystem that later
chipsets use, and type_vram is negative here, leading to an OOB memory
access.
This was previously guarded by a chipset check, restore that.
Reported-by: Thomas Zimmermann <[email protected]>
Fixes: 5839172f0980 ("drm/nouveau: explicitly specify caching to use")
Signed-off-by: Ben Skeggs <[email protected]>
Reviewed-by: Michael J. Ruhl <[email protected]>
Reviewed-by: Christian König <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions