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| author | Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2018-02-11 22:15:15 +0100 |
|---|---|---|
| committer | Felipe Balbi <felipe.balbi@linux.intel.com> | 2018-03-13 10:47:50 +0200 |
| commit | a5d411962c444377d0de0dc89502dbaf2e2a34e2 (patch) | |
| tree | a29d6d7def97d85d69a69d6d492520aa5a49a0a5 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | c1d5df69f55b997b327e68c24be43cf6686304bb (diff) | |
dt-bindings: usb: add support for dwc3 controller on Amlogic Meson GX
Amlogic Meson GX SoCs (GXL and AXG) come with a (host-only) dwc3 USB
controller. This requires a clock to be enabled and a reset line to be
pulsed to get the hardware into a known state.
Add the documentation for this IP block, similar to "qcom,dwc3.txt".
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Tested-by: Yixun Lan <yixun.lan@amlogic.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions