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| author | Stephen Boyd <sboyd@kernel.org> | 2024-04-29 14:59:35 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2024-04-29 14:59:35 -0700 |
| commit | a22549304372086420d0d5dc99661090e5c388b9 (patch) | |
| tree | c2000142dc35f0aa93c46f016ce799bb388df615 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | f8981b0d529513a78d30ae659b74269ae40fa2ab (diff) | |
| parent | 69f16d9b789821183d342719d2ebd4a5ac7178bc (diff) | |
Merge tag 'sunxi-clk-fixes-for-6.9-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes
Pull Allwinner clk driver fixes from Jernej Skrabec:
- fix H6 CPU rate change via reparenting
- set A64 MIPI PLL min & max rate
* tag 'sunxi-clk-fixes-for-6.9-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: a64: Set minimum and maximum rate for PLL-MIPI
clk: sunxi-ng: common: Support minimum and maximum rate
clk: sunxi-ng: h6: Reparent CPUX during PLL CPUX rate change
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions