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| author | Peng Ma <peng.ma@nxp.com> | 2024-02-01 16:50:07 -0500 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2024-02-07 09:31:49 +0100 |
| commit | 9d739bccf261dd93ec1babf82f5c5d71dd4caa3e (patch) | |
| tree | 3963d88085c95e8e11422d8b417594f600afc868 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | bbcc1c83f343e580c3aa1f2a8593343bf7b55bba (diff) | |
dmaengine: fsl-qdma: fix SoC may hang on 16 byte unaligned read
There is chip (ls1028a) errata:
The SoC may hang on 16 byte unaligned read transactions by QDMA.
Unaligned read transactions initiated by QDMA may stall in the NOC
(Network On-Chip), causing a deadlock condition. Stalled transactions will
trigger completion timeouts in PCIe controller.
Workaround:
Enable prefetch by setting the source descriptor prefetchable bit
( SD[PF] = 1 ).
Implement this workaround.
Cc: stable@vger.kernel.org
Fixes: b092529e0aa0 ("dmaengine: fsl-qdma: Add qDMA controller driver for Layerscape SoCs")
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20240201215007.439503-1-Frank.Li@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions