diff options
| author | Joel Stanley <[email protected]> | 2018-06-07 16:39:59 +0930 |
|---|---|---|
| committer | Stephen Boyd <[email protected]> | 2018-07-06 13:48:07 -0700 |
| commit | 974c7c6d7ba5a4b12d99456b0599aa6326dc2b69 (patch) | |
| tree | 2599c34f8f37481715ccfc29741a353903ea99b4 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | 53f3abe97b246ae8d36d868d5403bed057dfa4a7 (diff) | |
clk: aspeed: Mark bclk (PCIe) and dclk (VGA) as critical
This is used by the host to talk to the BMC's PCIe slave device. The BMC
is not involved, but the clock needs to be enabled so the host can use
the device.
Fixes: 15ed8ce5f84e ("clk: aspeed: Register gated clocks")
Cc: [email protected] # 4.15
Acked-by: Andrew Jeffery <[email protected]>
Tested-by: Lei YU <[email protected]>
Signed-off-by: Joel Stanley <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions