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authorLubomir Rintel <[email protected]>2018-11-13 11:22:26 +0100
committerMark Brown <[email protected]>2018-11-13 10:02:00 -0800
commit8ae13d0b0d4bb4af99bec8c50152f0c8f5cbcc06 (patch)
tree7c3c6366fbf1d3cffdbddb5dbd07a7e19c1376a4 /tools/perf/scripts/python/mem-phys-addr.py
parentec93cb6f827b3e1a81b0721b8c893d2a5e37e7d6 (diff)
spi: pxa2xx: dt-bindings: Add ready GPIO signal
This this is used to let the SPI master know that our FIFO is filled and we're ready to service a transfer. Only useful in slave mode. A signal like this is used by an embedded controller on a OLPC XO 1.75 machine, that happens to be a SPI master. Signed-off-by: Lubomir Rintel <[email protected]> Acked-by: Pavel Machek <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Mark Brown <[email protected]>
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