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authorAnusha Srivatsa <[email protected]>2022-11-17 15:00:02 -0800
committerAnusha Srivatsa <[email protected]>2022-11-21 15:19:50 -0800
commit86c0ef7234a7c517b010fd5ecf1e176127bce521 (patch)
tree045520629dc6d39faf5ea8754141def934f19cdd /tools/perf/scripts/python/mem-phys-addr.py
parent25e0e5ae561003817797c23ae3b85cf510be11c5 (diff)
drm/i915/display: Add CDCLK Support for MTL
As per bSpec MTL has 38.4 MHz Reference clock. Adding the cdclk tables and cdclk_funcs that MTL will use. v2: Revert to using bxt_get_cdclk() BSpec: 65243 Cc: Clint Taylor <[email protected]> Signed-off-by: Anusha Srivatsa <[email protected]> Reviewed-by: Clint Taylor <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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