diff options
| author | Jinzhou Su <[email protected]> | 2021-01-19 17:33:36 +0800 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2021-01-21 09:53:33 -0500 |
| commit | 860cc26a0179894648f031a6eab6945cb09bd796 (patch) | |
| tree | 2cd58dc8b029dd97cb9653f29f161e42908b0ee2 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | d96dd7ef3f347ce968a3d12d3e2c491592d8a84c (diff) | |
drm/amdgpu: Add RLC_PG_DELAY_3 for Vangogh
Driver should enable the CGPG feature for RLC in safe mode to
prevent any misalignment or conflict in middle of any power
feature entry/exit sequence.
Achieved by setting RLC_PG_CNTL.GFX_POWER_GATING_ENABLE = 0x1,
and RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG
hysteresis value in refclk count.
Reviewed-by: Huang Rui <[email protected]>
Signed-off-by: Jinzhou Su <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions