diff options
| author | Dmitry Baryshkov <[email protected]> | 2023-01-13 14:05:40 +0200 |
|---|---|---|
| committer | Bjorn Andersson <[email protected]> | 2023-01-18 22:50:01 -0600 |
| commit | 6fb03dd0b40aa83a3a04390ef539f1547b77ca1d (patch) | |
| tree | c89394e1ce6a7b7c8869a12d939c6a8e4979d6b8 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | fa0bc05f2f87eb84dba1977794048ee7b9ec6545 (diff) | |
clk: qcom: cpu-8996: fix PLL configuration sequence
Switch both power and performance clocks to the GPLL0/2 (sys_apcs_aux)
before PLL configuration. Switch them to the ACD afterwards.
Signed-off-by: Dmitry Baryshkov <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions