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authorAriel D'Alessandro <[email protected]>2021-11-19 12:32:46 -0300
committerMark Brown <[email protected]>2021-11-22 15:43:01 +0000
commit6e6752a9c78738e27bde6da5cefa393b589276bb (patch)
tree23c2ea4e00e3297320eb31466a01121cbc79cc45 /tools/perf/scripts/python/mem-phys-addr.py
parent2664b24a8c51c21b24c2b37b7f10d6485c35b7c1 (diff)
ASoC: tlv320aic31xx: Add divs for bclk as clk_in
Add divisors for rates needed when the clk_in is set to BCLK. Signed-off-by: Michael Trimarchi <[email protected]> Signed-off-by: Ariel D'Alessandro <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
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