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| author | Ville Syrjälä <[email protected]> | 2021-09-21 21:12:45 +0300 |
|---|---|---|
| committer | Ville Syrjälä <[email protected]> | 2021-09-24 15:54:29 +0300 |
| commit | 5f524aea39d9e2a74c063f340a77516e454badce (patch) | |
| tree | 57e660b76ac781d99331bdb72b813bf1bae99506 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | 2f051f6774bb8c6807b2287e6ca482089bd92364 (diff) | |
drm/i915/fbc: Implement Wa_16011863758 for icl+
There's some kind of weird corner cases in FBC which requires
FBC segments to be separated by at least one extra cacheline.
Make sure that is present.
v2: Respin to fit in with skl_fbc_min_cfb_stride()
v3: Make it build
Reviewed-by: Juha-Pekka Heikkila <[email protected]> #v1
Signed-off-by: Ville Syrjälä <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions