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| author | Srinivas Kandagatla <[email protected]> | 2022-06-09 12:19:00 +0100 |
|---|---|---|
| committer | Mark Brown <[email protected]> | 2022-06-10 13:32:14 +0100 |
| commit | 5babb012c847beb6c8c7108fd78f650b7a2c6054 (patch) | |
| tree | ff92ed61f2ffd8d96a0becb010f182bd63640470 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | 142d456204cf4dabe18be59e043d806440f609d4 (diff) | |
ASoC: codecs: msm8916-wcd-digital: move gains from SX_TLV to S8_TLV
move all the digital gains form using SX_TLV to S8_TLV, these gains are
actually 8 bit gains with 7th signed bit and ranges from -84dB to +40dB
rest of the Qualcomm wcd codecs uses these properly.
Fixes: ef8a4757a6db ("ASoC: msm8916-wcd-digital: Add sidetone support")
Fixes: 150db8c5afa1 ("ASoC: codecs: Add msm8916-wcd digital codec")
Signed-off-by: Srinivas Kandagatla <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions