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authorBoris Brezillon <[email protected]>2024-02-29 17:22:16 +0100
committerBoris Brezillon <[email protected]>2024-03-01 10:04:01 +0100
commit546b366600ef34847702f43bb2d22f914d19eae0 (patch)
treeef32cfd0ee87c627bf2fc1a8cdf7b226a630af16 /tools/perf/scripts/python/mem-phys-addr.py
parent0f25e493a2462dbdd2e34f4e100405380cc0201a (diff)
drm/panthor: Add GPU register definitions
Those are the registers directly accessible through the MMIO range. FW registers are exposed in panthor_fw.h. v6: - Add Maxime's and Heiko's acks v4: - Add the CORE_FEATURES register (needed for GPU variants) - Add Steve's R-b v3: - Add macros to extract GPU ID info - Formatting changes - Remove AS_TRANSCFG_ADRMODE_LEGACY - it doesn't exist post-CSF - Remove CSF_GPU_LATEST_FLUSH_ID_DEFAULT - Add GPU_L2_FEATURES_LINE_SIZE for extracting the GPU cache line size Co-developed-by: Steven Price <[email protected]> Signed-off-by: Steven Price <[email protected]> Signed-off-by: Boris Brezillon <[email protected]> Acked-by: Steven Price <[email protected]> # MIT+GPL2 relicensing,Arm Acked-by: Grant Likely <[email protected]> # MIT+GPL2 relicensing,Linaro Acked-by: Boris Brezillon <[email protected]> # MIT+GPL2 relicensing,Collabora Reviewed-by: Steven Price <[email protected]> Acked-by: Maxime Ripard <[email protected]> Acked-by: Heiko Stuebner <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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