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| author | Maciej W. Rozycki <[email protected]> | 2022-09-17 13:03:09 +0100 |
|---|---|---|
| committer | Bjorn Helgaas <[email protected]> | 2022-11-04 10:38:11 -0500 |
| commit | 503fa23614dc95f96af883a8e2e873d5c6cd53d8 (patch) | |
| tree | db370093acfd139e5bdb9cdaa188bffb936ad8d7 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | 9abf2313adc1ca1b6180c508c25f22f9395cc780 (diff) | |
PCI: Access Link 2 registers only for devices with Links
PCIe r2.0, sec 7.8 added Link Capabilities/Status/Control 2 registers to
the PCIe Capability with Capability Version 2.
Previously we assumed these registers were implemented for all PCIe
Capabilities of version 2 or greater, but in fact they are only
implemented for devices with Links.
Update pcie_capability_reg_implemented() to check whether the device has
a Link.
[bhelgaas: commit log, squash export]
Link: https://lore.kernel.org/r/[email protected]
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Maciej W. Rozycki <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions