diff options
| author | Nicholas Kazlauskas <[email protected]> | 2024-05-21 10:41:52 -0400 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2024-06-14 15:34:52 -0400 |
| commit | 470679ef332e7ebceb05d11e602d101a627e5200 (patch) | |
| tree | 778accb7d905a8d2bf9d01f5783fd2d06ff7906f /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | 06cd6d8f808164513e453af842720fe258abbbf0 (diff) | |
drm/amd/display: Guard reading 3DLUT registers for dcn32/dcn35
[Why]
3DLUT is not part of the DPP on DCN32/DCN35 ASIC and these registers
now exist in MCM state.
[How]
Add guards when reading DPP state based on whether the register has a
valid offset.
Reviewed-by: Sung joon Kim <[email protected]>
Acked-by: Zaeem Mohamed <[email protected]>
Signed-off-by: Nicholas Kazlauskas <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions