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authorFelix Fietkau <[email protected]>2018-07-30 21:31:28 +0300
committerKalle Valo <[email protected]>2018-07-31 10:52:25 +0300
commit461d8a6bb9879b0e619752d040292e67aa06f1d2 (patch)
treea37eb39e75d086ad5d45ef7ef45cc9b6be6c75fc /tools/perf/scripts/python/mem-phys-addr.py
parent1226f9e1029637ebdab6bd80928213b8c1ad965c (diff)
ath9k_hw: fix channel maximum power level test
The tx power applied by set_txpower is limited by the CTL (conformance test limit) entries in the EEPROM. These can change based on the user configured regulatory domain. Depending on the EEPROM data this can cause the tx power to become too limited, if the original regdomain CTLs impose lower limits than the CTLs of the user configured regdomain. To fix this issue, set the initial channel limits without any CTL restrictions and only apply the CTL at run time when setting the channel and the real tx power. Signed-off-by: Felix Fietkau <[email protected]> Signed-off-by: Kalle Valo <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
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