diff options
| author | Michael Walle <[email protected]> | 2021-01-20 20:43:03 +0100 |
|---|---|---|
| committer | Jakub Kicinski <[email protected]> | 2021-01-21 19:50:47 -0800 |
| commit | 43e5763152e2d4679954da0d35029637f017b0b3 (patch) | |
| tree | 9f0bdf98f78d966e3f3b9a8c31cd269235cb4c24 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | 19038523a7353e7413c5428f20376fa3ccd2c8e9 (diff) | |
net: macb: ignore tx_clk if MII is used
If the MII interface is used, the PHY is the clock master, thus don't
set the clock rate. On Zynq-7000, this will prevent the following
warning:
macb e000b000.ethernet eth0: unable to generate target frequency: 25000000 Hz
Signed-off-by: Michael Walle <[email protected]>
Reviewed-by: Andrew Lunn <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Jakub Kicinski <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions