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| author | Sakari Ailus <[email protected]> | 2020-06-05 22:46:54 +0200 |
|---|---|---|
| committer | Mauro Carvalho Chehab <[email protected]> | 2020-12-07 15:35:40 +0100 |
| commit | 415ddd9939783cb79790aba1833ea39fd335caed (patch) | |
| tree | 93ab16db937a70a20df6d44171656f8ef90ac5f5 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | c3833a228cef7121cb7fc64d5ef71eedcc6f2f01 (diff) | |
media: ccs-pll: Split limits and PLL configuration into front and back parts
The CCS spec supports a lot of variation in the PLL. Split the PLL in
front and back parts to better prepare for supporting it.
Also use CCS compliant naming for IP and OP PLL frequencies (i.e. include
"clk" in the name).
Signed-off-by: Sakari Ailus <[email protected]>
Signed-off-by: Mauro Carvalho Chehab <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions