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authorSascha Hauer <[email protected]>2022-04-14 18:22:31 +0200
committerMark Brown <[email protected]>2022-04-19 12:06:11 +0100
commit3ff84e3dd180c368981b2d58ed50f17a47471828 (patch)
tree23f2ad1c7555899a42a234e1799466400f3f4922 /tools/perf/scripts/python/mem-phys-addr.py
parent384672e3b7af65aaebb794a6d1a77bb975a10678 (diff)
ASoC: fsl_micfil: drop fsl_micfil_set_mclk_rate()
All that the .set_sysclk hook in the micfil driver does is to pass the sysclk frequency to fsl_micfil_set_mclk_rate(). This function expects the sample rate as argument though, not any kind of sysclk frequency. The resulting rate setting of the clock is overwritten in hw_params anyway, so drop this altogether. Signed-off-by: Sascha Hauer <[email protected]> Acked-by: Shengjiu Wang <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
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