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| author | Biju Das <[email protected]> | 2022-03-15 14:29:15 +0000 |
|---|---|---|
| committer | Geert Uytterhoeven <[email protected]> | 2022-04-04 10:58:46 +0200 |
| commit | 3733db1f77130588c9a2c1596937294998bd7d27 (patch) | |
| tree | 6e9c1267d91db096b458faf1de2abce80d24a6c4 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | 53367bd28f3bf143355e66f20cb6cb83b70e9122 (diff) | |
dt-bindings: clock: renesas: Document RZ/G2UL SoC
Document the device tree binding for the Renesas RZ/G2UL Type-1
and Type-2 SoC. RZ/G2UL Type-2 has fewer clocks than RZ/G2UL Type-1
SoC.
Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions