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| author | Andre Przywara <[email protected]> | 2022-11-07 00:54:24 +0000 |
|---|---|---|
| committer | Jernej Skrabec <[email protected]> | 2022-11-16 19:34:50 +0100 |
| commit | 30120faa1e8ee4725eb850d10ce2efdd29262a85 (patch) | |
| tree | 871981709f8eb645349d57c6a4b98092b9180c77 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | 1c50050ca1ebe46db27b016326c6c3508a161ee9 (diff) | |
dt-bindings: pwm: allwinner,sun4i-a10: Add F1C100s compatible
The PWM controller in the Allwinner F1C100s series of SoCs is the same
as in the A20 SoCs, so allow using that as the fallback name.
Join the V3s compatible string in an enum on the way.
Signed-off-by: Andre Przywara <[email protected]>
Acked-by: Rob Herring <[email protected]>
Acked-by: Thierry Reding <[email protected]>
Acked-by: Uwe Kleine-König <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Jernej Skrabec <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions