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| author | Xu Yilun <yilun.xu@intel.com> | 2020-06-11 11:25:06 +0800 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2020-06-15 23:36:01 +0100 |
| commit | 3011d314751535782508a86bbd8de415ea99909f (patch) | |
| tree | 032bcba612b8f1af536f39fe80103bf08e3056a6 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | 064e8af7159539fc2310870841e7f215b4f633e9 (diff) | |
spi: altera: add 32bit data width transfer support.
Add support for 32bit width data register, then it supports 32bit
data width spi slave device and spi transfers.
Signed-off-by: Xu Yilun <yilun.xu@intel.com>
Signed-off-by: Wu Hao <hao.wu@intel.com>
Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Signed-off-by: Russ Weight <russell.h.weight@intel.com>
Reviewed-by: Tom Rix <trix@redhat.com>
Link: https://lore.kernel.org/r/1591845911-10197-2-git-send-email-yilun.xu@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions