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| author | Rohit Agarwal <[email protected]> | 2022-02-22 10:26:21 +0530 |
|---|---|---|
| committer | Bjorn Andersson <[email protected]> | 2022-03-08 16:17:40 -0600 |
| commit | 2cabc45237659cb3b0294c8b8ae12f5fd0dad28d (patch) | |
| tree | d9af2f98e440e4eec215285ac005c8b0fbec6cb2 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | 013804a727a0482bc6661e15dfababde5f856550 (diff) | |
dt-bindings: clock: Add A7 PLL binding for SDX65
Add information for Cortex A7 PLL clock in Qualcomm
platform SDX65.
Signed-off-by: Rohit Agarwal <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions