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authorDave Jiang <[email protected]>2023-02-14 10:00:24 -0700
committerDan Williams <[email protected]>2023-02-14 14:12:54 -0800
commit248529edc86f8d7d390a15a86bd1904951311665 (patch)
tree0eb11c11d179bca096a9c8539a3dd02bbe39c1d3 /tools/perf/scripts/python/mem-phys-addr.py
parent1922a6dc0502ed3fd0786f57cc9e5f515c902009 (diff)
cxl: add RAS status unmasking for CXL
By default the CXL RAS mask registers bits are defaulted to 1's and suppress all error reporting. If the kernel has negotiated ownership of error handling for CXL then unmask the mask registers by writing 0s. PCI_EXP_DEVCTL capability is checked to see uncorrectable or correctable errors bits are set before unmasking the respective errors. Acked-by: Bjorn Helgaas <[email protected]> # pci_regs.h Reviewed-by: Jonathan Cameron <[email protected]> Signed-off-by: Jonathan Cameron <[email protected]> Signed-off-by: Dave Jiang <[email protected]> Link: https://lore.kernel.org/r/167639402301.778884.12556849214955646539.stgit@djiang5-mobl3.local Signed-off-by: Dan Williams <[email protected]>
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