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authorDaniel Machon <[email protected]>2024-10-24 00:01:20 +0200
committerJakub Kicinski <[email protected]>2024-10-30 18:08:04 -0700
commit1ebaa5e189151a396de3fcd280078eaf7b922920 (patch)
tree5f093b0c66d1f6e8682bad417cab7cea4a43d7c5 /tools/perf/scripts/python/mem-phys-addr.py
parent4ddf7ccfdf70364010005b0b695b1a0d92677425 (diff)
net: sparx5: add support for lan969x targets and core clock
In preparation for lan969x, add lan969x targets to sparx5_target_chiptype and set the core clock frequency for these throughout. Lan969x only supports a core clock frequency of 328MHz. Also, set the policer update internal (pol_upd_int) matching the 328 MHz frequency of the lan969x targets. Reviewed-by: Steen Hegelund <[email protected]> Signed-off-by: Daniel Machon <[email protected]> Link: https://patch.msgid.link/20241024-sparx5-lan969x-switch-driver-2-v2-1-a0b5fae88a0f@microchip.com Signed-off-by: Jakub Kicinski <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
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