diff options
| author | Claudiu Beznea <[email protected]> | 2023-10-16 13:53:43 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <[email protected]> | 2023-11-20 09:19:06 +0100 |
| commit | 00cbba479142a3c962a44b127db4ab6cdc2b2b70 (patch) | |
| tree | e9b36211e1d84911d15a82a73529be317a58d376 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | 51dad0523b1e94493c9dd8596bd4a9d0d88d8fcb (diff) | |
arm64: dts: renesas: rzg3s-smarc-som: Enable SDHI2
Add SDHI2 to RZ/G3S Smarc SoM. SDHI2 pins are multiplexed with SCIF1,
SSI0, IRQ0, IRQ1. The selection b/w SDHI2 and SCIF1, SSI0, IRQ0, IRQ1
is done with a switch button. To be able to select b/w these a
compilation flag has been added (SW_SD2_EN) at the moment being
instantiated to select SDHI2.
Signed-off-by: Claudiu Beznea <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions