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authorShengjiu Wang <[email protected]>2022-06-17 15:44:37 +0800
committerMark Brown <[email protected]>2022-06-27 13:18:11 +0100
commite3f4e5b1a3e654d518155b37c7b2084cbce9d1a7 (patch)
treef320c27e02c6bed045c8812f86ed013835752c69 /tools/perf/scripts/python/libxed.py
parent6b878ac2711056dd07c712caf89f58449cf5a592 (diff)
ASoC: fsl_sai: Configure dataline/FIFO information from dts property
The SAI has multiple successive FIFO registers, but in some use case the required dataline/FIFOs are not successive, so need get such information from dts property "fsl,dataline" fsl,dataline has 3 values for each configuration: first one means the type: I2S(1) or DSD(2), second one is dataline mask for 'rx', third one is dataline mask for 'tx'. Also set dma peripheral address and TRCE bits according to data lane. Signed-off-by: Shengjiu Wang <[email protected]> Signed-off-by: Viorel Suman <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
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