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author | Lad Prabhakar <[email protected]> | 2022-10-28 17:59:16 +0100 |
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committer | Geert Uytterhoeven <[email protected]> | 2022-11-10 15:59:03 +0100 |
commit | 9f643dc28e2c072d7d323898530ee37433e74595 (patch) | |
tree | cbe572bef22696282e0248d201a5eec881a35735 /tools/perf/scripts/python/libxed.py | |
parent | 57e1b873c2f54253f4c81bddb782e183ee6544ae (diff) |
dt-bindings: riscv: Add Andes AX45MP core to the list
The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP
Single) from Andes. In preparation to add support for RZ/Five SoC add
the Andes AX45MP core to the list.
More details about Andes AX45MP core can be found here:
[0] http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/
Signed-off-by: Lad Prabhakar <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
Reviewed-by: Guo Ren <[email protected]>
Acked-by: Palmer Dabbelt <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/libxed.py')
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