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| author | Aidan MacDonald <aidanmacdonald.0x0@gmail.com> | 2022-03-17 00:07:40 +0000 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2022-03-24 20:10:32 +0100 |
| commit | 9279c00fa40250e5cb23a8423dce7dbc6516a0ea (patch) | |
| tree | 47f5f58ac7e1701b0eda5c0de1c9a0c4210293c7 /tools/perf/scripts/python/libxed.py | |
| parent | 283fb4ea08c5876150b4158e9c20c14309214ce2 (diff) | |
pinctrl: ingenic: Fix regmap on X series SoCs
The X series Ingenic SoCs have a shadow GPIO group which is at a higher
offset than the other groups, and is used for all GPIO configuration.
The regmap did not take this offset into account and set max_register
too low, so the regmap API blocked writes to the shadow group, which
made the pinctrl driver unable to configure any pins.
Fix this by adding regmap access tables to the chip info. The way that
max_register was computed was also off by one, since max_register is an
inclusive bound, not an exclusive bound; this has been fixed.
Cc: stable@vger.kernel.org
Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Fixes: 6626a76ef857 ("pinctrl: ingenic: Add .max_register in regmap_config")
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20220317000740.1045204-1-aidanmacdonald.0x0@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/libxed.py')
0 files changed, 0 insertions, 0 deletions