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authorNeil Armstrong <[email protected]>2023-11-14 11:14:43 +0100
committerJerome Brunet <[email protected]>2023-11-24 18:03:00 +0100
commit439d3404addf1a1ee8ba6dc6becd555bce7faf98 (patch)
tree9c7ed65e74f556845e733c017396c26d317a5f49 /tools/perf/scripts/python/libxed.py
parentbd5ef3f21d17a80d4e5b9c8e18bad20c8fb53c95 (diff)
dt-bindings: clock: g12a-clkc: add MIPI ISP & CSI PHY clock ids
Add MIPI ISP & CSI PHY clock ids to G12A clock bindings header Signed-off-by: Neil Armstrong <[email protected]> Acked-by: Conor Dooley <[email protected]> Reviewed-by: Daniel Scally <[email protected]> Tested-by: Daniel Scally <[email protected]> Link: https://lore.kernel.org/r/20231114-topic-amlogic-upstream-isp-clocks-v1-1-223958791501@linaro.org Signed-off-by: Jerome Brunet <[email protected]>
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