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authorJouni Högander <[email protected]>2024-05-17 10:30:04 +0300
committerJouni Högander <[email protected]>2024-05-20 07:34:45 +0300
commit30dee753ca0a1b565da5eec8d0686315f595d171 (patch)
treef0c42b4e0c208288da4d08453ee79a8848c58488 /tools/perf/scripts/python/libxed.py
parent45430e7b7c8de9ed910d99cc8906db3db5a1334d (diff)
drm/i915/psr: LunarLake PSR2_CTL[IO Wake Lines] is 6 bits wide
On LunarLake PSR2_CTL[IO Wake Lines] contains now bit 13:18. Take this into account when enabling PSR2_CTL. Bspec: 69885 Signed-off-by: Jouni Högander <[email protected]> Reviewed-by: Uma Shankar <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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