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authorSergio Paracuellos <[email protected]>2021-08-22 18:10:03 +0200
committerGreg Kroah-Hartman <[email protected]>2021-09-21 17:30:55 +0200
commit159697474db41732ef3b6c2e8d9395f09d1f659e (patch)
tree66fb760f743e4670417629c208474e88ae39e75e /tools/perf/scripts/python/libxed.py
parent51a72ec705dfa7f5ae2a70041cdbc53804ba6ee8 (diff)
MIPS: ralink: don't define PC_IOBASE but increase IO_SPACE_LIMIT
Defining PCI_IOBASE results in pci resource handling working but the addresses generated for IO accesses are wrong since the ioremap in the pci core function 'pci_parse_request_of_pci_ranges' tries to remap to a fixed virtual address (PC_IOBASE) which can't work for KSEG1 addresses. To get it working this way, we would need to put PCI_IOBASE somewhere into KSEG2 which will result in creating TLB entries for IO addresses, which most of the time isn't needed on MIPS because of access via KSEG1. So avoid to define PCI_IOBASE and increase IO_SPACE_LIMIT resource for ralink MIPS platform instead, to get valid IO addresses for resources from pci core 'pci_address_to_pio' function. Fixes: 222b27713d7f ("MIPS: ralink: Define PCI_IOBASE") Acked-by: Thomas Bogendoerfer <[email protected]> Signed-off-by: Sergio Paracuellos <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
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