diff options
| author | Vidya Sagar <[email protected]> | 2022-10-14 00:08:41 +0530 |
|---|---|---|
| committer | Vinod Koul <[email protected]> | 2022-10-28 17:43:12 +0530 |
| commit | 0983529d7513e5417a5010f70582e1040c404551 (patch) | |
| tree | 93e514fd49507801a957af04ef297ab864416f3c /tools/perf/scripts/python/libxed.py | |
| parent | 38cd167d1fc6b5bf038229b1fa02bb1f551a564f (diff) | |
phy: tegra: p2u: Set ENABLE_L2_EXIT_RATE_CHANGE in calibration
Set ENABLE_L2_EXIT_RATE_CHANGE register bit to request UPHY PLL rate change
to Gen1 during initialization. This helps in the below surprise link down
cases,
- Surprise link down happens at Gen3/Gen4 link speed.
- Surprise link down happens and external REFCLK is cut off, which causes
UPHY PLL rate to deviate to an invalid rate.
Signed-off-by: Vidya Sagar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/libxed.py')
0 files changed, 0 insertions, 0 deletions