diff options
| author | Jiri Pirko <[email protected]> | 2024-10-30 09:11:57 +0100 |
|---|---|---|
| committer | Jakub Kicinski <[email protected]> | 2024-11-03 08:39:07 -0800 |
| commit | e2017f27b6f888fb4ebc5c9a6d984bbf2f8b99ff (patch) | |
| tree | 0e2e4e44c21a6e494893e858ad22ebc0b47c0355 /tools/perf/scripts/python/intel-pt-events.py | |
| parent | a1afb959add1fad43cb337448c244ed70bac3109 (diff) | |
net/mlx5: DPLL, Add clock quality level op implementation
Use MSECQ register to query clock quality from firmware. Implement the
dpll op and fill-up the quality level value properly.
Reviewed-by: Arkadiusz Kubalewski <[email protected]>
Signed-off-by: Jiri Pirko <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Jakub Kicinski <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/intel-pt-events.py')
0 files changed, 0 insertions, 0 deletions