diff options
| author | Daniel Machon <[email protected]> | 2024-10-24 00:01:22 +0200 |
|---|---|---|
| committer | Jakub Kicinski <[email protected]> | 2024-10-30 18:08:05 -0700 |
| commit | 728267dc46d3bbb21bf9431ecbb6c8e9251cd711 (patch) | |
| tree | f574b30edf821833494d433a8468eb276549b39e /tools/perf/scripts/python/intel-pt-events.py | |
| parent | 9324881cef519acee1d7b187fd9ed0f92fb28fe2 (diff) | |
net: sparx5: change frequency calculation for SDLB's
In preparation for lan969x, rework the function that calculates the SDLB
(Service Dual Leacky Bucket) clock. This is required, as the
HSCH_SYS_CLK_PER register is Sparx5-exclusive. Instead derive the clock
from the core clock, using the sparx5_clk_period() function. The clock
stays the same before and after this patch, only now,
sparx5_sdlb_clk_hz_get() can be used for lan969x too.
Reviewed-by: Steen Hegelund <[email protected]>
Signed-off-by: Daniel Machon <[email protected]>
Link: https://patch.msgid.link/20241024-sparx5-lan969x-switch-driver-2-v2-3-a0b5fae88a0f@microchip.com
Signed-off-by: Jakub Kicinski <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/intel-pt-events.py')
0 files changed, 0 insertions, 0 deletions