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| author | Laurent Pinchart <[email protected]> | 2020-07-01 16:48:53 +0300 |
|---|---|---|
| committer | Vinod Koul <[email protected]> | 2020-07-01 19:36:57 +0530 |
| commit | 574ba3667891b432f92478a02f686bb779a1e593 (patch) | |
| tree | ef8d15b3b827489e24418c6eaf1a2f8c1c7bd526 /tools/perf/scripts/python/intel-pt-events.py | |
| parent | 4a33bea003144e217d8a3ae666f171dfc2e97bd6 (diff) | |
dt-bindings: phy: zynqmp-psgtr: Fix example's numbers of cells in reg
The DT examples are by default compiled in a parent that has
#address-cells and #size-cells both set to 1. Fix the example
accordingly, even if it doesn't match the actual hardware, as this is
the recommended practice for DT bindings examples.
Fixes: cea0f76a483d ("dt-bindings: phy: Add DT bindings for Xilinx ZynqMP PSGTR PHY")
Signed-off-by: Laurent Pinchart <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/intel-pt-events.py')
0 files changed, 0 insertions, 0 deletions