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authorBen Widawsky <[email protected]>2017-09-20 11:35:24 -0700
committerRodrigo Vivi <[email protected]>2017-09-26 13:02:44 -0700
commit4e9767bc28e93139442847f023ff2fc0c2a21d34 (patch)
tree9a5fd8afce32d9f6baae006b3321146763bfc890 /tools/perf/scripts/python/intel-pt-events.py
parent4d34b11e46184bb5762491d32566fade188c6c01 (diff)
drm/i915/cnl: Add support slice/subslice/eu configs
Cannonlake Slice and Subslice information has changed. This patch initially provided by Ben adds the proper sseu initialization. v2: This v2 done by Rodrigo includes: - Fix on Total slices count by avoiding [1][2] and [2][2]. - Inclusion of EU Per Subslice. - Commit message. v3: This v3 done by Rodrigo includes: - Handle all possible bits and extra fuse register. - Use INTEL_GEN macro. - Fully assume uniform distribution so remove union with eu_per_subslice and add proper the comment. v4: This v4 done by Rodrigo includes: - Consider all bits available: 6 bits for slices [27:22] and 4 for subslices [21:18]. v5: This v5 done by Rodrigo includes: - sseu->subslice_mask = (1 << 4) - 1 - missed on previous versions and noticed by Oscar. Cc: Oscar Mateo <[email protected]> Signed-off-by: Ben Widawsky <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]> Reviewed-by: Oscar Mateo <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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